designer & engineer
BS Computer Engineering @ UP Diliman.
I build systems and the visuals that explain them.
I'm Jam — a computer engineering student with a dual background in graphic design and machine learning research. I've led design for school publications, run a freelance brand design practice, interned in data science doing smart meter analytics, and presented ML research at IEEE TENCON 2025 in Malaysia. I care about work that's both functional and well-crafted.
Architected an adaptive ML pipeline for QUIC traffic intrusion detection, processing 390,000 flows through dynamic feature selection, an Adaptive Random Forest online classifier, and ADWIN drift detection — achieving a 99.94% recall rate and <0.1% FPR.
A network of three sensor nodes deployed in EEEI using STM32 NUCLEO-F411RE, monitoring temperature, smoke, and infrared radiation via DS18B20, MQ2, and KY-026. Data is transmitted via ESP8266 to ThingSpeak and visualized in Google Sites, with a buzzer alarm triggered when thresholds are reached. Features battery backup for resiliency during power outages.
An RFID-controlled access system for EEEI labs built on NodeMCU ESP8266, using an RFID-RC522 reader and RTC module for time-based authentication. Entry and exit logs are written to Google Sheets in real-time via Google Apps Script, with class schedules synced through Google Calendar. Features LED access indicators and battery backup.
Designed and implemented a custom VGA display controller on the Arty A7-35T FPGA, rendering a 160×120 image at 640×480 @ 60Hz via a Digilent Pmod VGA module. Integrated block RAM (VRAM) initialized with the EEEI logo and connected to a MicroBlaze processor via AXI BRAM Controller. A rotary encoder peripheral handles real-time horizontal translation, vertical translation, and 90° image rotation with wraparound.
Benchmarked a Rust ray tracer across 11 test scenes on a local Intel i7 and Repl.it, using time profiling to identify render() as the primary bottleneck. Applied function-level optimizations and compiler release profiles, achieving up to 50x speedup — reducing Scene 5 from 1,506s down to 3.2s.
Benchmarked and optimized a multi-layer perceptron inference pipeline on a PIC32CM microcontroller with no hardware FPU. Stage 1 eliminated redundant loops and temp allocations; Stage 2 converted to Q11 fixed-point arithmetic, achieving a 23.2× speedup over baseline — reducing mean inference from 149,118μs to 6,434μs — while maintaining 100% correctness.
Logo suites, typography systems, and marketing collateral for clients. Previously ran a customized vector art shop on Shopee. Also led design for PSHS-CLC's Bahaghari publication and PhiSciCLaban creatives committee.